The present disclosure relates in general to managing signal noise in electronic circuits. More specifically, the present disclosure relates to systems, methodologies and resulting structures for efficiently embedding discrete decoupling semiconductor devices (e.g., capacitors) in substrates, cores and/or printed circuit boards (PCBs) to reduce on-package high frequency noise.
As the supply voltages of processor systems (e.g., a central processor unit (CPU)) decrease into the sub-volt range, achieving power integrity is increasingly difficult. For example, in a processor system that uses a 1.2V power supply having +/−5% noise tolerance, a maximum 120 mV peak-to-peak power noise level may be acceptable. However, if the power supply voltage is reduced to 0.9V, the same maximum 120 mV peak-to-peak power noise level now represents a +/−7% variation, which can cause intolerable system errors in many processor system designs.